Instruction execution in typical data processors is partitioned into functional routines. These routines perform either a portion of the instruction or the entire instruction, depending on the instruction's complexity. The major categories of functional routines in current data processors are effective address evaluation and the operation itself. An example is the fetch effective address routine which calculates an effective address and then fetches the sized operand from that address. To perform this operation, it is necessary to provide size information during the address calculation operation to determine the amount to autoincrement and autodecrement the address register for predecrement and postincrement addressing modes. The size is also needed by the bus controller to determine the size of the operand to be fetched from memory. These routines require that the instruction be decoded to reflect the size of the operand to be fetched. Similarly, the instruction operation routine which performs the operation on the operands for the instruction may require their size.
In a machine which performs operations on various sized operands that is controlled by a control structure, it is possible to provide different control sequences for each sized operation. This technique is inefficient, however, for while it is necessary to provide separate control for those operations larger than the size of the available resources, all sizes less than or equal to those resources should share control sequences and allow secondary decoding of the instruction and provide the determination as to which size should occur.
As long as the only sharing of control sequences that takes place concerns the size of the operation there is little difficulty in this approach. However, if there is sharing of code sequences for multiple operations as well as multiple operand sizes, the constraints become more stringent. As an example, there are functional routines provided to evaluate an effective address and to fetch the sized operand. In typical data processors having a 16 bit data bus in current data processors, there are two different routines, one to fetch a long word operand and the other to fetch a byte or a word operand depending upon the size of the operation. These routines can be called in the execution of any instruction.
For example, previous data processors, such as Motorola's M68000 and M68010, perform operations on operands which have their size or length specified as part of the instruction. The size of the operation normally reflects the size of the operand to be operated on for an instruction. There are three operand sizes handled in these processors, namely 8-, 16- and 32-bit operands to perform byte, word and long word operations, respectively. The control used to perform sized operations is derived from the instruction and affects the execution unit, condition codes in the condition code register, the data bus and the bus controller.
When the instruction is decoded, the operations are divided into two categories: long operations and byte/word operations. Because the internal bus, arithmetic units and external data bus are typically 16 bits wide, 16 bits is the maximum natural operand size. It follows that in this scheme, long word operations are performed as two 16 bit operations. The size of the individual operations performed in these previous data processors is always 16 bits for long word operations, and is usually 16 bits in most other cases.
Thus, in general, there are certain resources or parameters which determine the size of the micromachine, regardless of the architecture implemented. By using the initial entry decode to segregate long word operations from other operations, the problem of how to control the execution unit, the data bus and the other size sensitive units is reduced from three types of data sizes to two, i.e. long word and word/byte.
In these previous processors, byte and word operations share control store sequencing. This means that the same microroutines are used to control both byte and word sized operations. Thus, it is necessary for those units which are sensitive to size to be directly provided with this information.
The determination as to whether the size of the operation is byte or word is made by residual decoding of the instruction. The instruction is decoded to determine whether the operation is byte or word. If the instruction size is byte, then a signal is asserted to indicate that this is a byte operation to the size sensitive units. Even though an instruction is sized as byte, not all operations associated with that instruction are byte operations. There may be elements of the byte sized instruction, such as instruction fetch and address calculation which need to be performed as 16 or 32 bit operations. At the start of a byte operation, the microcontroller will enable the residual decoder to provide the decoded size specification to the size sensitive units. For 16- or 32-bit operations, the microcontroller will disable the residual decoder. In this way, a byte operation is specified only if it is decoded as a byte operation in the residual decoder and if the residual decoder is enabled by the nanocontroller. This procedure implies that the only method for specifying a byte operation is to have the instruction decoded as a byte operation in the residual decode.
For a further description of how sizes are specified in these prior art data processors, see U.S. Pat. No. 4,307,445 and U.S. Pat. No. 4,488,228.